A framework for 1-D compaction with forbidden region avoidance [VLSI layout]

In this paper we consider the I-dimensional compaction problem when the layout area contains forbidden regions and the layout components are allowed to move across these regions. Assume we are given a feasible layout containing k forbidden regions and n layout components, where the i-th layout component is a rectilinear polygon consisting of Vi vertical edges, v = L~l Vi· We present an algorithm that determines the positions of the layout components resulting in minimum area in O((J' log (J' + (J'n log n) time with an 0((v + k) log k+ (v + (J') log v) preprocessing time. The quantity (J' measures the interaction between the layout components and the forbidden regions, (J' ~ vk. We also describe variants ofthis algorithms that make the running time more problem-dependent and consider forbidden regions of special structure. Our algorithms make use of an elegant characterization of a layout of minimum area. "Research supported in part by ONR under contracts N00014-84-K-0502 and N00014-86K-0689, and by NSF under Grant MIP-87-15652. tResearch supported in part by NSF under Grant MIP-87-15652 and ONR under contract N00014-84-K-0502.